Neural network implementation of a binary adder

摘要

A binary adder is provided for adding-processing in a high speed parallel manner two N bit binary digits. The binary adder is implemented using neural network techniques and includes a number of amplifiers corresponding to the N bit output sum and a carry generation from the result of the adding process; an augend input-synapse group, an addend input-synapse group, a carry input-synapse group, a first bias-synapse group a second bias-synapse group an output feedback-synapse group and inverters. The binary adder is efficient and fast compared to conventional techniques.