| 摘要 |
PURPOSE:To miniaturize an FSK signal decoder, to realize non-adjustment, and to attain inexpensive constitution by providing an edge detecting means, plural shift registers, an AND gate, and an OR gate. CONSTITUTION:The edge detecting means 1 outputs a pulse synchronized with the timing of an input FSK signal, and supplies it to an edge detection circuit 2, and the output of the circuit 2 is shifted with the shift registers 3 of N stages. Next, the output of the circuit 2 and the registers 3 are supplied to the AND gate 4, and are AND-computed, and that of the gate 4 is supplied to the OR gate 6 via the shift registers 5 of M stages. And an output signal in which the dense side of an FSK signal goes to logic 0 or 1 is outputted from the gate 4 by selecting the number of stages of the register 3 conforming to a shift pulse frequency supplied to the register 3. Also, the output signal in which the coarse side of the FSK signal goes to the logic 1 or 0 is outputted by selecting the number of stages of the register 5. In such a way, the FSK signal decoder can be miniaturized, and the non-adjustment and low pricing can be attained. |
