| 摘要 |
PURPOSE:To obtain stable operation by providing a frequency comparator, which uses a bistable circuit and is suitable for LSI-implementation, with a flip-flop which inverts an output terminal level when an insignificant pulse which does not inverts the output of the bistable circuit is inputted. CONSTITUTION:A reference pulse B is inputted to a terminal B. When a pulse A is not inputted to a terminal A, a flip-flop 14 is reset by the pulse B. A D flip- flop 18 is triggered at every leading edge of the pulse B, but never changes because a delay terminal D2 is at an ''L''. When the pulse A is inputted, the flip- flop 14 is set at its leading edge. At the leading edge of the pulse B, the D flip- flop 18 is triggered and its output is inverted. At the trailing edge of the pulse A, the flip-flop 14 is inverted. Even if the leading edge of the pulse A is inputted before the arrival of the pulse B, the couput of a D flip-flop 15 never changes. |
