发明名称 VARIABLE DELAY CIRCUIT
摘要 PURPOSE: To enable adjustment of a delay at high resolution during a period between minimum and maximum delays by adjusting the gain of 1st and 2nd amplifiers. CONSTITUTION: When the gain of a 1st amplifier A1 is high and the gain of a 2nd amplifier A2 is low, a load current and an output from a delay circuit are changed at their states after a minimum delay almost equal to the propagation time of the 1st amplifier A1. When the gain of the 1st amplifier 1 is low and the gain of the 2nd amplifier A2 is high, the states of the load current and the output of the delay circuit are changed, after a maximum delay which is almost equal to the sum of propagation time values of a buffer and the 2nd amplifier A2. The status change delays of a load signal IL and an output signal from the delay circuit following the status change of an input signal are adjusted at high resolution during the period between the minimum and maximum delays, by adjusting the gain of the amplifiers through a control signal.
申请公布号 JPH03108812(A) 申请公布日期 1991.05.09
申请号 JP19880297997 申请日期 1988.11.25
申请人 TEKTRONIX INC 发明人 RASUZURO JIYONASU DOBOSU
分类号 H03H11/26;H03K5/00;H03K5/13;H03K17/60;H03K17/62;H03K19/003 主分类号 H03H11/26
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