| 摘要 |
<p>PURPOSE:To optimize the relation of phase without readjustment of wiring length even when the characteristic of a timing extraction circuit is in dispersion with each device by applying automatic adjustment of the phase between a data signal and a clock signal in an identification regeneration circuit. CONSTITUTION:When the trailing of a clock signal 34 is delayed by t with respect to the leading of an equalized amplification signal 32, an up-down counter 23 catches a high level state of the clock signal 34 at the timing of leading of the equalizing amplification signal 32, a count output 36 is incremented by 1, converted into an analog value 37 by a D/A converter 24, inputted to a phase variable circuit 25, and a control voltage of the phase variable circuit 25 is increased by V. Thus, the relation of the phase of the clock signal 34 and the equalized amplification signal 32 approaches an optimum point. The identification regeneration circuit 22 applies identification regeneration of the equalizing amplification signal 32 based on the clock signal 34 adjusted to the optimum point automatically to output an identification regeneration data signal 38.</p> |
