Cache memory access system with a memory bypass for write through read operations.

摘要

The present invention utilizes bypass6circuitry to shorten the cycle time of a cache memory (300) by shortening the time required to perform a write through read operation (WTR). The bypass circuitry senses when a WTR operation will occur by comparing the encoded read and write addresses to determine when the encoded addresses are equal. When the encoded addresses are equal, a WTR operation is requested and the bypass circuitry sends the data to be written into memory to both the write address location and the cache output buffer. The bypass circuitry does not wait to access the data from the memory cells through the read decode, rather, it directly sends the data to the output buffer. The bypass circuitry provides a parallel read and write operations instead of serial operations during a WTR, thereby shortening the machine cycle time. The bypass circuitry also prevents glitches from being sent to the output when the WTR operation is complete by accessing the memory cells through the read decode even though the cells are disconnected from the output buffer during the WTR operation. The cycle time is shortened by making the longest operation of the memory shorter.