| 摘要 |
<p>When a data read timing of a DMAC (3) is not matched with an output timing of data read out from a DRAM (1), the readout data is held in a register (6) until a subsequent data read timing of the DMAC comes to the front. When data is read out from the DRAM, and if a processor clock of the DMAC has a phase matched with that of an operation clock of the DRAM, then a direct read operation is performed. If the phases of the two clocks are not matched with each other, the readout data from the DRAM (1) is temporarily stored in the register and then fetched in the DMAC (3).</p> |
