发明名称 DATA ERASING METHOD FOR SEMICONDUCTOR MEMORY
摘要 <p>PURPOSE:To eliminate problems of small number of rewriting times, a large current and to obtain an erasing method using a tunnel current by floating one diffused layer, grounding a control gate and applying a voltage for blocking flow of an avalanche current between the other diffused layer and a substrate. CONSTITUTION:In a data erasing method for a semiconductor device in which a MOS transistor having a control gate 18 and a floating gate 16 is used as a memory unit, one diffused layer 14 is so floated that a current does not flow from either one diffusion layer 14 forming the source 14 or the drain 13 of the MOS transistor to a substrate 11, the gate 18 of the transistor is grounded, a voltage Vd for blocking the flow of an avalanche current is applied between the other diffused layer 13 of the transistor and the substrate 1, and a potential stored at the gate 16 is removed. For example, the source 14 is floated, and a pulse of 12.75V is simultaneously applied to both the drain 13 and a P-type well 12 for 10msec.</p>
申请公布号 JPH03108772(A) 申请公布日期 1991.05.08
申请号 JP19890302233 申请日期 1989.11.22
申请人 OKI ELECTRIC IND CO LTD 发明人 TSUJIMOTO MASAO;ONO TAKASHI
分类号 G11C17/00;G11C16/04;G11C16/06;H01L21/8247;H01L27/115;H01L29/788;H01L29/792 主分类号 G11C17/00
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