发明名称 |
Dynamic semiconductor memory device having reduced soft error rate |
摘要 |
Each of sense amplifiers is coupled to two bit lines with another bit line being interposed therebetween. Information stored in a memory cell is read out onto one of the two bit lines coupled to each of the sense ampliers, while a reference potential is read out onto the other bit line. Outside of the two bit lines, a reference potential is respectively read out onto other bit lines adjacent to the two bit lines. The information stored in the memory cell is read out onto the other bit line between the two bit lines.
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申请公布号 |
US5014241(A) |
申请公布日期 |
1991.05.07 |
申请号 |
US19890337219 |
申请日期 |
1989.04.12 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
ASAKURA, MIKIO;FUJISHIMA, KAZUYASU;MATSUDA, YOSHIO |
分类号 |
G11C11/401;G11C5/02;G11C5/06;G11C7/14;G11C7/18;G11C11/4096;G11C11/4097;G11C11/4099;H01L21/8242;H01L27/108 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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