| 摘要 |
<p>PURPOSE:To decrease time-base errors by providing an output port which inputs one master latch part to a slave latch circuit in response to the coincidence signal between one comparison data register and the counted value of a free- running counter. CONSTITUTION:Data on the time difference up to a target point of time when an output signal having a series of signal patterns begins to be sent is sent out of the output port to a data bus 1200 and stored in the comparison data register 1111. Further, time difference data of output signals which are sent out successively corresponding to respective time intervals are stored in registers 1112 - 1114 through a bus 1200. Then data to be outputted at the set time stored in those registers are stored in master latches 1141 - 1144 through the bus 1200. Consequently, the output signal having a series of signal patterns with a small error is obtained from the output port 1100.</p> |
