| 摘要 |
<p>A logic controlled delay circuit (305) is connected into the arbitration logic (155) of a computer system of the type having a main data bus (115) which is subject to control by multiple masters (140). The delay is so programmed that the default master, which is the main processor (CPU) (100) for the system and is assigned the residual or default priority, is assured a predefined portion of the time available on the bus (115). By so inserting and controlling the delay that the "hold" signal to the CPU (100) is delayed whenever the CPU (100) is granted access to the bus (115) , other devices, are unable to seize the bus (115) until the delay has ended at which time the CPU (100) is triggered by the delayed signal to respond with an acknowledge which serves to permit arbitration to begin. By this technique a standard microprocessor such as an Intel 80386 can operate in such an architecture without being preempted from the bus (115) by the higher priority devices (140) to an extent that system operation deteriorates.</p> |
