发明名称 TDM-PKT CONVERSION CIRCUIT
摘要 <p>PURPOSE:To reduce the delay in conversion at a fast data speed and to reduce the quantity of buffer by switching a storage plane of a double buffer for storing signals on a time division multiplex bus where data of a different speed exist in mixture at the switching speed corresponding to each data speed. CONSTITUTION:A write control section 1 switches storage planes at write in buffers 31, 32 at a switching speed in response to the line speed and writes a data on a TDM bus to a relevant area of a selected buffer in response to line number information of a time division multiplex(TDM) control section 4. Moreover, a readout control section 2 selects storage planes for readout of the buffers 31, 32 in response to the line speed and reads out a prescribed quantity of th data in an area corresponding to the buffers in response to the line number from a packet(PKT) control section 5. Thus, the required buffer capacity is reduced and the conversion delay is decreased.</p>
申请公布号 JPH03106149(A) 申请公布日期 1991.05.02
申请号 JP19890241845 申请日期 1989.09.20
申请人 FUJITSU LTD 发明人 KAMIYA YOSHIMASA;KAJIWARA TAKAHARU
分类号 H04L12/56;H04L12/66 主分类号 H04L12/56
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