| 摘要 |
<p>In a delay measuring circuit (10), an input clock signal (13) is applied to a multitapped delay line (14), the output taps of which are connected to a switch (26) which selects one of the switch inputs for connection to a phase comparator (34) which compares the input clock signal (13), delayed in a delay device (38) to compensate for the delay inherent in the switch (26), with the output of the switch (26). The input clock signal is also applied to a counter (22), and when the phase comparator (34) detects a phase match, the counter value is stored in a latch (32), the counter 122) is reset to a predetermined value, and the counting procedure resumed. The latch (32) thus always stores a value dependent on the delay of an individual delay cell (16-1 to 16-N). This stored value can be applied to various uses, such as in a timing watchdog circuit or for generating accurate delays.</p> |
