| 摘要 |
<p>PURPOSE:To exclude an unbalance component of a balance signal fundamentally by providing 1st and 2nd differential amplifiers having an input output characteristic respectively and a logic gate section applying a prescribed operation to an output corresponding to the balance signal. CONSTITUTION:The circuit is provided with 1st and 2nd differential amplifiers 21, 22 receiving a balance signal Sin in common and having the 1st input output characteristic biased negatively and the 2nd input output characteristic biased positively and provided with a logic gate section 23 passing the logic of an output Lout of a differential amplifier 10 as it is when an input voltage is zero V and at the outside of a bias range BS biased in the vicinity and interrupting the passing of the output Lout within the bias range BS and sending an alarm signal. Thus, an unbalance component of the balance signal flowing by connecting a resistance to the balanced input is fundamentally excluded.</p> |
