发明名称 DATA COMMUNICATION EQUIPMENT
摘要 <p>PURPOSE:To reduce the time of serial communication by using a bit length setting means to set a start bit location and an end bit location of a data and using a high speed dummy clock for other periods (dummy periods) thereby attaining the serial communication of a data with an optional bit length. CONSTITUTION:A bit 2 is set to a bit length setting register section 2 as a start value and a bit 4 is set as a stop value. Then the serial communication is initiated to cause a clock control section 2 to start shifting and counting with a dummy clock not required for the serial communication. When a comparison detection section 9 detects the coincidence between the start value and the count, the clock control section 2 switches the shift clock and the shifting and counting are implemented by using the serial communication shift clock. When the output of the data of bit 4 is finished, the comparison detection section 9 detects the coincidence between the stop value and the count, an output control section 10 disables the output thereby stopping the output of a data and a shift clock.</p>
申请公布号 JPH03104459(A) 申请公布日期 1991.05.01
申请号 JP19890242675 申请日期 1989.09.19
申请人 FUJITSU LTD 发明人 OZAWA YUKIHIRO
分类号 G06F13/38;G06F13/42;H04L7/00;H04L7/04;H04L29/08 主分类号 G06F13/38
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