| 摘要 |
PURPOSE:To prevent the inverting timing of a biphase clock signal, from being overlapped even when a power voltage is fluctuated by providing a clock generating circuit comprising a couple of gate circuits, a detection circuit and a timing adjustment circuit. CONSTITUTION:When a power voltage VDD rises and a voltage V1 reaches a threshold level of an inverter 19 as a detection circuit or over, its output goes to a low level and an output of an inverter 20 goes to a high level. Thus, transfer gates forming a timing adjustment circuit are turned off and transfer gates 13, 17 are turned on. Then an output of NOR gates 1, 2 being components of the clock generating circuit is given to one input of the gates 2, 1 via inverters 11, 12, the gate 13, inverters 15, 16 and the gate 17. As a result, the output is delivered to the other gate after trailing of the output of either gate 1, 2 and after being retarded in the inverters 11, 12 or 15, 16 and the biphase clock signal whose inverting timings are not overlapped even when the power voltage is fluctuated is generated to prevent malfunction. |
