| 摘要 |
PURPOSE:To shorten the time required for data generation and the time required for write and replacement of an EPROM by writing parity check data in a memory which can be read and written by hardware. CONSTITUTION:The address generated by an address counter 6 is inputted to an EPROM 2 for program and a readable and writable memory 8, where parity check data is stored, through a selector 7. Data outputted from the EPROM 2 for program is inputted to a parity generating circuit 3, and parity data is written in the memory 8 for parity through the selector 7 by a parity writing circuit 9. The selector 7 is switched to check parity data outputted from the memory 8 for parity and data from the parity generating circuit 3 by a parity check circuit 5 in the same manner with respect to the address generated by a CPU 1. Thus, the labor of generation of parity check data, write to the EPROM 2, and replacement is reduced. |
