| 摘要 |
<p>PURPOSE:To reduce the circuit scale and to improve the resolution by providing a holding circuit and a selector which couples first and second counter parts. CONSTITUTION:When carry input signals CI1 to CIn are '1', counters 2-1 to 2-n are counted down synchronously with clock signals KA and KB and output carry output signals CO1 to COn, and they are latched in a first holding circuit 3-1. They are selected by a selector 3-2 synchronously with timing signals T11, T12..., and a select carry output signal ECO1 is inputted to a second counter part 4 as a first carry part. The select carry output signal ECO1 of carry output signals CO1 to COn from counters 2-1 to 2-n of a first counter part 2 and count data DReg,1 to DReg,2 of the second counter part 4 are added, and the counted value is sent to a data bus BUS. Thus, the circuit scale is reduced and the resolution is improved.</p> |
