| 摘要 |
The present circuit incorporates a latch which latches an asynchronous input signal and provides a latched output signal to the first stage of a two stage synchronizer. An AND gate receives the latched output signal and the output from the first stage such that the output signal from the AND gate follows the output of the first synchronizer and is presented as an input to a second stage of the two stage synchronizer. The second stage is clocked, as is the first stage, with the system clock signal to provide the synchronized output signal. An asynchronous reset of the latch causes the output of the AND gate to go low which in turn causes the output of the second stage to go low asynchronously.
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