| 摘要 |
PURPOSE:To eliminate the variation of the delay time of an output signal from a reset release signal by delaying the release of the resetting of one flip flop compared to that of the other flip flop and setting a threshold as against the reset release signal of the flip flop to a different value so as to realize the time difference. CONSTITUTION:When FET of Vth=O[V] is used for the flip flop(FF), the ratio of the gate widths of FET 51 and 52 in the D-type flip flop(DEF) 31 is set to 1.5:1.0, and the ratio of the gate widths of the other FF 32-38 is to 1:1, for example. Thus, the threshold of DFF 31 as against the reset release signal becomes high compared to the threshold of the other FF 32-33. Thus, the output of a dual modulus pre-scaler (PSC) 6 appears after prescribed time from the release of the resetting of DFF 31 without fail and it does not depend on the order of the reset release of the other FF 32-38. Then, time till the leading-in of a frequency and the establishment of synchronization is shortened. |
