| 摘要 |
PURPOSE:To prevent erroneous data from being reproduced by extracting the timing component of a data signal at a reception side and reproducing the data. CONSTITUTION:When a transmission side sends the data signal and a clock signal, the data signal is inputted to an input terminal 1 and connected to the data input section of a flip-flop 4. On the other hand, the clock signal is inputted to an input terminal 2 and a timing extraction circuit extracts the timing and its output signal is converted into a TTL level at a rectangular wave conversion circuit 6, connected to the clock input section of a flip-flop 4 and the data signal is regenerated. Thus, no noise pulse or distorted clock exists in the clock signal due to crosstalk between signal lines and the data signal is regenerated without error. |
