| 摘要 |
PURPOSE:To easily change the scale of a system by using information concerning a fault and the recognition number of a processor when the arbitrary processor or the bus of a data transfer network breaks down. CONSTITUTION:When the fault is generated on the bus of data transfer from a processor P[j,k] to a processor P[k,i], the processor P[k,i] confirms the error of receiving data or the fault with the processor P[k,j] as the transfer source of the data which are not transferred. As the fault information, three- dimensional information [j,k,i] for a buffer memory unit BMU of a data transfer network 20 are notified to all the processors of a processor array. Afterwards, according to the information of a mask register 27, an address generating circuit 26 of a transmission/reception controller SRU successively generates addresses skipping the address of the j-th BMU. Accordingly, as the whole system, the system due to the two-dimensional arrangement processor array of (N-1)X(N-1) is constructed excepting for the processor in the j-th row and the processor in the i-th column. |
