发明名称 PROGRAM DOWN LOADING TYPE EMULATOR
摘要 PURPOSE:To debug software/hardware even if a program can not be transferred from the host side by providing the emulator with a down loading circuit and previously transferring the program from a program memory in a target to an instruction memory in the emulator. CONSTITUTION:The emulator 1 is constituted of the same processor 4 as that of the target 2, a memory storing RAM 5 for the processor 4, a program transferring down loading circuit 10, and so on. Prior to debugging, the contents of the program are previously transferred from the program memory 9 in the target 2 by the down loading circuit 10. The operation is applied to the whole program address space of the whole program address space of the processor 4 at a slow speed by which no problem is generated in the delay of a cable. Even when the program can not be transferred from the host 3, the software/ hardware of the target 3 can be debugged.
申请公布号 JPH0399334(A) 申请公布日期 1991.04.24
申请号 JP19890235922 申请日期 1989.09.12
申请人 FUJITSU LTD 发明人 OIKAWA SHIGEO
分类号 G06F11/22 主分类号 G06F11/22
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