| 摘要 |
PURPOSE:To attain the test with a minimum number of test patterns by connecting a hardware to a multi-stage synchronous counter so as to surely grasp the state transition of the counter. CONSTITUTION:With a test signal at an H level inputted to a test terminal, a test data generating circuit 2 and a load signal generating circuit 3 are brought into the test state. A load signal whose period is half the period of a clock signal is sent from the circuit 3 to a counter circuit 1 to be tested and the circuit 1 is set initially at the leading of the clock signal and a '0000' signal is fed back to the circuit 2 to conduct the countup test of the circuit 1 at the leading of a succeeding clock signal and a test device 4 applies count test to the counter output of '0001'. Then the load and countup are repeated sequentially to conduct the countup test for each bit. When the test of the most significant digit is finished and the data output of the circuit 1 is '1111', the circuit 1 sends a carryout signal and the test of the least significant bit '0000' is conducted. |
