发明名称 MULTIPORT MEMORY
摘要 PURPOSE:To reduce energy consumption by controlling access operation from an input/output port in one part to a static form and controlling access operation from the remaining input/output port to a dynamic form. CONSTITUTION:A first control circuit 3 to control the access operation through an input/output port 4 in one part to the static form, which always select word lines WL1i and WL2i while following up the change of an input address signal, a second control circuit 7 to control the access operation through a remaining input/output port 8 to the dynamic form which synchronizes the operation to a clock are provided. In a data input/output system to be dynamically interfaced, a current does not flow from a bit line loading element through the selection register of a memory cell 10 and further the driving register of the memory cell 10 normally in a chip selecting state. Thus, the energy consumption can be reduced.
申请公布号 JPH0395795(A) 申请公布日期 1991.04.22
申请号 JP19890231130 申请日期 1989.09.06
申请人 HITACHI LTD;HITACHI VLSI ENG CORP 发明人 HATANO SUSUMU;OOISHI TSURATOKI;KITANO JUN;NISHIMOTO KENJI;NAGASHIMA YASUSHI;KIKUCHI TAKASHI;SAIKOU YASUHIKO;FURUNOMA TOSHIHIKO;SASAKI KOTOKO;UCHIYAMA KUNIO;AOKI HIROKAZU;NISHII OSAMU
分类号 G11C11/41 主分类号 G11C11/41
代理机构 代理人
主权项
地址
您可能感兴趣的专利