| 摘要 |
<p>PURPOSE:To miniaturize a cosine conversion device and to attain a high processing speed equivalent to that of an independent conversion circuit by sharing perfectly all arithmetic circuits used for the cosine conversion and the inverse cosine conversion. CONSTITUTION:The selectors S1 - S5 select the side of a terminal P in an FCT mode. Thus the eight data x0 - x7 inputted from an INPUT terminal are inputted to an arithmetic clock A via the terminal P of the selector S1. An 8-point butterfly addition is carried out at the block A. Then the higher 4 bytes are inputted to an arithmetic block B via the terminal P of the selector S2. At the same time, the lower 4 bytes are inputted to an arithmetic block D via the terminal P of the selector S4. The data inputted to the block B undergo a 4-point butterfly addition and are inputted to an arithmetic block C via the terminal P of the selector S3. The data inputted to both blocks C and D undergo the operations of each block and are outputted via the terminal P of the selector S5 as the data x0 - x7 undergone the cosine conversion.</p> |
