| 摘要 |
PURPOSE:To reduce gate resistance, reduce gate capacity, improve resistance to high temperature process and improve high frequency characteristics by a method wherein a metallic layer having high melting point is made wider than a metal silicide layer having high melting point. CONSTITUTION:Length along a MOSFET channel length and lateral length as widths of respective layers of a three-layered gate electrode are specified so that the width of a molybdenum silicide layer 13 is smaller than that of a metal molybdenum layer 14. The width of a gate region is determined by width of an electrode 16 formed on a semiconductor substrate 11 while width of the gate region corresponds to a distance between N<+>-type diffusion layers 17, 18 to be a source and a drain regions. The distance corresponds to width of a layer 14 to be a substantial ion implantation mask when both regions are to be formed by ion implantation or the like. |
