| 摘要 |
<p>A pipelined multi-stage ADC in which residue signals are passed between stages as currents. All sample-and-hold circuits are designed to be current-in/current-out structures; all but one also provide a voltage output. A voltage representation of the analog signal is provided as input to the flash converter within the quantization loop of each stage, allowing implementation of a conventional voltage comparator architecture in the flash converter. An extra comparator is added to the flash converter and an extra segment is included in the DAC of each stage. Inputs above full scale and below zero can be converted and generate output codes. Whenever the input goes above full scale or below zero, an out-of-range bit is set and the digital outputs are set to all ones or all zeroes, respectively. The combination of out-of-range bit and digital codes tell whether overranging or underranging occurred.</p> |
