发明名称 Data signal conversion into binary, frequency shifted output signal - generates both output signal frequencies by different division of clock pulse signal
摘要 The data signal consists of binary parts forming data words. The two output signal frequencies are formed by different divisions of a clock pulse signal, which simultaneously serves for the entire circuit synchronisation. The binary parts are serially used for determining the respective dividing ratio. The circuit has a control (SE), a controllable frequency divider (UT) and a clock pulse signal source (TQ). The latter is coupled both to the control clock pulse input and the frequency divider signal input. The control input is linked to the circuit input, and its output is coupled to the frequency divider control input. The divider signal output is coupled to the circuit output. USE/ADVANTAGE - For NC machine tool control etc., with standard components for high reliability.
申请公布号 DE3934643(A1) 申请公布日期 1991.04.18
申请号 DE19893934643 申请日期 1989.10.17
申请人 SIEMENS AG, 1000 BERLIN UND 8000 MUENCHEN, DE 发明人 ARNDT, KARSTEN, 6300 GIESSEN, DE
分类号 G11B20/14;H04L7/033 主分类号 G11B20/14
代理机构 代理人
主权项
地址