| 摘要 |
A Bi-CMOS logic circuit includes a Bi-CMOS circuit which is composed of first and second bipolar transistors (Q1, Q2), first and second resistors (R1, R2) and first and second MOS transistors (MP1, MN1). An input signal (IN) is applied to the gates of the first and second MOS transistors, and an output signal (OUT) is drawn from a connection node where the first and second bipolar transistors are connected in series between first and second power sources. A third MOS transistor (MP2) is connected between the collector and emitter of the first bipolar transistor. The input signal is applied to the gate of the third MOS transistor. In place of or in addition to the third MOS transistor, a fourth MOS transistor (MN2) is provided which is connected between the collector and emitter of the second bipolar transistor. The third and fourth MOS transistors function to decrease roundings of rising and falling edges of the waveform of the output signal. |
