| 摘要 |
<p>An address buffer circuit for a dynamic memory comprises a flip-flop (FF), connected at one input/output terminal (N,) with first input circuitry (IN,) in parallel with third input circuitry (IN3), and at its other input output terminal (N2) with second input circuitry (IN2) preferably in parallel with fourth input circuitry (IN4). The second input circuitry receives a reference voltage (REF) and is activated by a timing clock (ØON), during a normal operation mode. The first input circuitry is activated by an external address timing clock (ØON) and receives an external address (ADD). The third input circuitry receives an internal refresh address (R) and is activated by an internal refresh address timing clock (ØOR). The address buffer (17) cooperates with a switcher which produces the internal refresh address timing clock (ØOR) and the external address timing clock (ØON) alternatively, by switching a basic timing clock generated by an address drive clock generator. Such a circuit can enable higher operating speeds to be achieved.</p> |
