| 摘要 |
PURPOSE:To obtain sufficient setting-up time and holding time receiving a calculated output even in the case of driving a multiplier device using a high speed clock signal, also to miniaturize the device and to reduce the cost of the device by adding 1st-3rd delay circuits to the device. CONSTITUTION:Among the data to be inputted to a multiplier circuit 1, the ones which take a long time before calculation are started are inputted after being delayed at the 1st and 2nd delay circuits 12, 13 to shift a calculation cycle to be delayed in time. Also, a calculated result which is decided quickly at the multiplier circuit 1 is outputted after the timing is delayed by a 3rd delay circuit 14, and is delayed until the other calculated results are decided. Thus, sufficient time for receiving all calculated results is secured, correspondence to even the drive by the high speed clock becomes possible, and since the calculation can be executed by using the adder of array system with less part numbers compared with a CLA type adder, etc., the miniaturization of the device and the reduction of the cost can be attained. |
