HIGH SPEED SCRAMBLING AT LOWER CLOCK SPEEDS

摘要

Circuitry generates a plurality of differentlyphase ?-sequences (or pseudo-random sequences) for scrambling/descrambling of all tributary data signals at a multiplexer/demultiplexer. By scrambling/descrambling at the tributary levels and thus at the lower tributary clock rates, less complex circuitry can be employed, and by properly selecting the tributary scrambling sequences in accordance with the teachings of this invention, a desired high speed line sequence can be attained.