| 摘要 |
PURPOSE:To simplify the hardware and to attain high speed data transmission by providing host computer, a transmission control computer executing a protocol such as a transmission control protocol, a communication control circuit and plural common memories or the like. CONSTITUTION:A host computer 1 generates a transmission data at first at the time of transmitting the packet data and stores it in a common memory 6 and issues a transmission request to a transmission control computer 2 via an FIFO 5. The computer 2 based on the transmission request generates a head data according to an HDLC protocol, and stores the data in a common memory 7, sets an address for a head data and an information data to an address control register of a DMA control circuit 10 to start the circuit 10. The circuit 10 supplies the head data and the information data sequentially a communication control circuit 11 according to the content of the address control register to send the data. That is, since only the computers 1, 2 attain data transmission with less overhead of transmission control, high speed data transmission is realized with less hardware. |
