| 摘要 |
PURPOSE:To obtain a stable PLL against a variation of the duty ratio of a clock, by providing a flip-flop which is set by a polarity variation point of an input digital signl and is reset by an output clock of a voltage control oscillator. CONSTITUTION:At a time T3, a polarity variation point of a digital signal (a) go ahead of its stable point. Therefore, in a state of the third H level of a Q-output (f) of a flip-flop FF7, time width of its H level increases as compared with time width in case of time T1, T2. Therefore, a differenrial amplifier 8 outputs negative voltage of this increased time width. On the contrary, at a time T4, the polarity variation point of the digital signal (a) lags the stable point a little, therefore, the diffenential amplifier 8 outputs positive voltage (g). In this way, it is possible to obtain a PLL for outputting a clock (c) synchronizing with the polarity variation point of the digital signal (a). |
