| 摘要 |
PURPOSE:To stably generate continuous clock pulses by comparing the pulse input with a feed back pulse obtained by delaying the phase of a reference clock when the input of discontinuous clock pulses to a phase comparator exists, and controlling the extent of delay of the phase of the reference clock pulse to control synchronization. CONSTITUTION:When a pulse missing signal from a pulse missing detecting circuit 3c is inputted, the signal from a phase comparator 3a is ignored and the output value to a delay circuit 3d is fixed. An output clock pulse f'o of a PLL circuit 3e obtained by delaying the phase of a reference clock pulse fi is used as the feedback pulse to the phase comparator 3a, and the extent of delay of the reference clock pulse fi dependent upon an up/down counter 3b and the delay circuit 3d is controlled with respect to the lead and lag of the phase, and a read clock pulse f'o which has the same phase as and is continuous to a discontinuous clock pulse fo outputted from a comparator 2 is outputted from the PLL circuit 3e. |
