| 摘要 |
The generator oscillator (2) has its reference frequency (fr) generated in a synthesiser (6) in a directly digital synthesis. The synthesiser output frequency (fR) is mixed high in a mixture (8) and reduced to a reference frequency value by a frequency divider such that the secondary wave increase in the oscillator PLL is compensated by secondary wave reduction during division of the synthesiser output frequency. - The oscillator PLL contains an adjustable frequency divider (4), whose max. adjustable dividing factor (N) pref. equals the dividing ratio (M) of the other frequency divider for the synthesiser output frequency division. |
