发明名称 |
Bitline precharge circuit of multi-sectional memory array |
摘要 |
The invention relates to a bit line precharge circuit of a multi-sectional memory array in which a first set of circuits gate a section decoding signal and a main bit line precharge pulse and a second set of circuits gate the section decoding signal and a main data line precharge pulse. The resultant signals from the first and second sets of circuits are fed into respective inverter circuits and then respectively into a bit line precharge circuit and a data line precharge circuit so that the operation margin of the section decoding signal increases by as much as the width of the main bit line precharge pulse.
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申请公布号 |
US5007023(A) |
申请公布日期 |
1991.04.09 |
申请号 |
US19890348213 |
申请日期 |
1989.05.05 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM, BYEONGYUN;HWANG, SANGKI |
分类号 |
G11C11/41;G11C7/12;G11C8/18;G11C11/419;G11C16/06;G11C17/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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