| 摘要 |
PURPOSE:To exclude significant delay to the logical operation at the time of returning an ECL output circuit to the general logical operation by invalidating the general logical operation of the ECL output circuit only at the time of wiring test and merging a wiring test logical value setting circuit part in the ECL output circuit. CONSTITUTION:An ECL output circuit 14 is provided where transistors TRs 10 and 12 for wiring test are connected to a TR branch 6, which receives the logical input voltage of the internal logical output in a first package 2 by the logical input, and the other TR branch 8 respectively. A control circuit 23 for wiring test which supplies complementary logical values to both on/off control inputs in accordance with the wiring test logical value setting control logical value supplied to the input is provided for the purpose of performing the wiring test between an output pin 18 and an input pin 21 of a second package 4. Thus, the number of circuit elements required for the wiring test is reduced to exclude the delay of a general logical signal. |
