| 摘要 |
PURPOSE:To prevent an object to be tested from synchronizing to a inversion reset signal and erroneously shifting to the test mode by making an input terminal of inversion test signal forcibly to be a specified signal level when the inversion reset signal is supplied. CONSTITUTION:Since output data supplied from an A flip-flop circuit 1 are latched at the rise of clock signal X0 by a B flip-flop circuit 2, output data sent out from the circuit 2 are changed to be an L-level from the time T2. So, a transmission gate 33 is made to be ON from the time T2 and the input terminal 30 of inversion test signal is made to be an input state from the time T2. Then the signal level is made to be a H-level at the time T2 which is delayed timewise from the time T1, i.e. the time when the terminal 30 is made to be the input state. Consequently, the time when the test mode setting circuit is actually reset at the time T0' when the inversion reset signal is changed to the L-level, is not the time T0' but to be T2. The device for test mode setting circuit is never erroneously brought into the test mode state accordingly. |
