发明名称 FRAME SYNCHRONIZATION TRANSMISSION TIMING SYSTEM
摘要 PURPOSE:To simplify the constitution of a hardware by realizing by a firmware a fact that when a frame synchronization patter is detected, a bit of receiving data is counted, and at the time point when it reaches a prescribed counting value, the transmission timing notice is executed. CONSTITUTION:An 8-bit data receiving circuit 21 brings input receiving data to series-parallel conversion and inputs parallel data of 8 bits to an 8-bit general microprocessor 23, and also, executes an 8-bit receiving interruption notice to the microprocessor 23. On the other hand, whenever receiving data is detected by 1 bit, a 1-bit reception detecting circuit 22 executes the 1-bit receiving interruption notice to the microprocessor 23. The microprocessor 23 realizes a reception processing, a frame synchronization detection, a bit count processing and a transmission processing by a firmware processing.
申请公布号 JPH0380728(A) 申请公布日期 1991.04.05
申请号 JP19890218060 申请日期 1989.08.24
申请人 FUJITSU LTD 发明人 SHOJI JUNJI
分类号 H04L29/08;H04L7/00;H04L7/08 主分类号 H04L29/08
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