发明名称 Control of cache memory - using validity bit change after delay to protect memory content against falsification
摘要 An on chip dynamic RAM memory is used as a cache memory in data processing systems and has data written into it in the form of working data together with a validity bit. The validity bit has to be reset after a specific delay period before the working data can be accessed. This prevents any changes or falsification of the data during the period. The cells of the memory are based upon capacitive elements and the validity bit change is determined by the charge period. ADVANTAGE - Controls working data against changes.
申请公布号 DE3932103(A1) 申请公布日期 1991.04.04
申请号 DE19893932103 申请日期 1989.09.26
申请人 SIEMENS AG, 1000 BERLIN UND 8000 MUENCHEN, DE 发明人 BREINTNER, RICHARD, DIPL.-ING., 8261 AMPFING, DE;ERNST, ROLAND, DIPL.-ING., 8000 MUENCHEN, DE;GROSSMANN, HEIN-PETER, 8024 DEISENHOFEN, DE;KOLARZ, THOMAS, DIPL.-MATH., 8000 MUENCHEN, DE;WAHR, ALFONS, DIPL.-INFORM., 8080 FUERSTENFELDBRUCK, DE
分类号 G06F12/08;G11C7/20;G11C11/404;G11C11/4072 主分类号 G06F12/08
代理机构 代理人
主权项
地址