| 摘要 |
The invention relates to a controllable, temperature-compensated voltage limiter with a pnp or npn semiconductor structure in which the width and doping of the central region are such that, when a voltage is applied to the two outer layers, no avalanche or Zener effect occurs (punch-through diode). According to the invention, the voltage UB to be limited is applied between the blocking pn junction (B-C). In addition, an adjustable auxiliary voltage (UH) is applied between the other pn junction (H-C). It is possible by means of the auxiliary voltage UH to set the punch-through at a higher value, so that this value is largely temperature-independent. |
