| 摘要 |
<p>Process for fabricating a high-voltage MIS integrated circuit. This process for fabricating an integrated circuit containing MIS transistors whose sources (18, 32) and drains (20, 34) consist of double junctions and whose gates are formed in a semiconductor layer, comprises a first implantation of ions (14) of a specified conductivity type in the semiconductor substrate, at a specified dosage, in order to form therein first source (18) and drain (20) junctions, and then a second implantation of ions (30) of the same type as the first, at a higher dosage than that of the first implantation in order to form the said double junctions; this process is characterised in that, between the first and second implantations, a conducting layer (28) is epitaxially formed on the said first junctions (18, 20) and on the gates (8a), the second implantation being formed across this epitaxied layer so that the double junctions are formed therein in part. <IMAGE></p> |
