| 摘要 |
An integrated circuit for convolution type computations of the form <IMAGE> where j-i+k, and j and k are integers and i is a natural integer, Ci being complex coefficients and Xj being complex or real input data, for use in digital signal processing. A plurality of cells are connected in a sequence, all receiving simultaneously the input data; the complex coefficients are subsequently sent on a propagation bus to a cell first in the sequence of connected cells. Each cell includes a multiplier, and an adder accumulator, and a transfer circuit for transferring received coefficients to the next cell. In each cell, sequentially received coefficients are first used for computation and then transferred by the transfer circuit with a suitable delay. A logic device controls the time distribution and repetition of the real and imaginary parts of the input data. The cells alternately perform partial computations on the real and imaginary parts; the results, with a corresponding validations signal, are pooled by a pooling circuit and applied to a common results-framing and rounding circuit.
|
