| 摘要 |
The circuit can select the mode like page, nibble, or static column mode easily without metal masking or wire bonding change in the nega bit level DRAM. A first power source (1) is connected with a second power source (o) through a metal (2), PMOS FET (4), fuse (6), and NMOS FET (12) connected in series. The PMOS FET is controlled by a first latch (17) controlled by a pad (21) level and a NMOS FET (14) controlled a reset circuit (19). A NMOS FET (12) is controlled by the output level of the reset circuit inputting the chip enable clock (20) through a delay circuit (13). A second latch (8) controlled by the NMOS FET (12) provides the output to a mode selector (11) through a buffer (10). The second latch (8) may be controlled directly by the first power source (1) when removing the metal and fuse.
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