METHOD OF DIVIDING AN INPUT-OUTPUT LINE BY DECODING

摘要

The method is for reducing the I/O load transmitting time having been increased as the integration rate grows up in the DRAM design. The circuit drived by a pair of bit lines (B/L) divides a pair of I/ O lines (I/O) connected to a sense amplifier (1). A sub I/O line (2) is connected to the pair of bit lines through first transistors (M4-5). A main I/O line (3) is connected to the output node of the I/ O lines (2) through second MOS transistor (M6-7). The I/O lines (2) are switchable with the decoding signal applied to the first transistors. The main I/O lines (3) are switchalbe with the second decoding signal applied to the second transistors after the first decoding signal is applied to the first transistors.