发明名称 CLOCK SIGNAL REGENERATING SYSTEM
摘要 PURPOSE:To regenerate an external data output clock from a reception signal of a data transmission channel by outputting a frame synchronizing signal, and regenerating a data output clock signal from the frame synchronizing signal. CONSTITUTION:Utilizing a ratio of a period of a frame synchronizing signal and a period of an external data outputting clock is constant in average, and only the phase of both the signals is asynchronous; the frame synchronizing signal S3 is multiplied and smoothed by a phase synchronizing circuit 8 to recover a data outputting clock CLK. Then a demodulated data series S7 is extracted of only information bit by a data conversion section 6 and outputted by a clock CLK as an external output data S0. Thus, the external data outputting clock regenerator is obtained with simple device constitution without deteriorating the utilizing rate of the frequency.
申请公布号 JPH0370228(A) 申请公布日期 1991.03.26
申请号 JP19890204613 申请日期 1989.08.09
申请人 HITACHI LTD;YUUSEISHIYOU TSUSHIN SOGO KENKYUSHO 发明人 OKANE TAKEO;SASAOKA SHUICHI;SANPEI MASAICHI;KAMIO YUKIHIDE;SHIMURA TAKANORI;TSUKAMOTO NOBUO;USUI KUNITO
分类号 H04J3/06;H04L7/02 主分类号 H04J3/06
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