| 摘要 |
PURPOSE:To reduce the number of logic ICs and to improve its cost economy by providing first-second groups of time constant circuits and comparators, and generating a dead time. CONSTITUTION:A dead time generator for an inverter controller has a first group of time constant circuits 10 for delaying the falls of PWM signals (U-W- phases) output from an I/O port of a control unit 3 by a time constant C.R, a second group of time constant circuits 11 for delaying the rise of the PWM signal by a time constant C.R, and first and second groups of comparators 12, 13 for comparing them with a reference value. A dead time is provided between the PWM signals obtained from the comparators 12, 12. As a result the number of ICs can be reduced. |
