发明名称 DIGITAL PHASE SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To generate a clock, which can send a transmission signal of less jitter to a home device and has less jitter, in an intra-office terminating equipment by providing a master clock oscillator, a frequency division ratio designating circuit, a variable frequency dividing circuit, or the like. CONSTITUTION:The master clock from a master clock oscillator 1 has the frequency normally divided by N in a variable frequency dividing circuit 2 to generate an output clock, and this output clock is outputted to a fixed frequency dividing circuit 3. The circuit 3 outputs the inputted clock to a phase comparing circuit 4 after frequency division, and the circuit 4 compares its phase with the phase of the reference clock extracted from a network. The frequency division ratio of the circuit 2 is changed by a frequency division ratio designating circuit 5 in accordance with the comparison result to synchronize the phase. In this case, a frequency fM of the master clock is set to satisfy fM=f0XN+ or fM =f0XN- where f0 is the nominal frequency of the output clock. Thus, the frequency in occurrence of jitter is reduced to improve the circuit characteristic.
申请公布号 JPH0368232(A) 申请公布日期 1991.03.25
申请号 JP19890204065 申请日期 1989.08.07
申请人 FUJITSU LTD 发明人 ISHII YOSHINORI
分类号 H04L7/033 主分类号 H04L7/033
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